Communication system for video information apparatus

ABSTRACT

A communication system for video information apparatus for carrying out a communication between a video information apparatus and a peripheral apparatus arranged so that a communication is repeatedly carried out at a period synchronized with a signal of a vertical period having a constant phase relation relative to a vertical synchronizing signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to bidirectional communication between a singlemaster apparatus and a plurality of slave apparatus and, moreparticularly but not exclusively, to a method and apparatus forcommunication between video information apparatus, such as VTR (videotape recorder) or video disc player, and peripheral apparatus, such astuner, a timer, a video camera, editing apparatus, a computer and so on.

2. Description of the Prior Art

Recently, in order to enhance the enjoyment of video equipment, a videoinformation system has been developed, which comprises a VTR as masterapparatus and a plurality of peripheral or slave apparatus, such as.Iadd.a video .Iaddend.camera, a television tuner unit, a timer unit and.Iadd.editing .Iaddend.apparatus. In such a system, the communication ofcontrol data, such as a mode signal and various other control signals,between the VTR and each peripheral apparatus becomes a significantproblem.

In a system for bidirectional communication between a VTR used as masterapparatus and a plurality of peripheral apparatus each used as a slaveapparatus, it is important that the number of communication lines bereduced as much as possible. This becomes increasingly important as thenumber of slave apparatus is increased.

A bidirectional communication system having at the side of the masterapparatus only two communication lines one of which is a transmissioncommunication line and the other of which is a reception communicationline has much to recommend it. Alternatively, a bidirectionalcommunication system having only one communication line may be employed.

The assignee of the present application has previously proposed abidirectional communication system using only one communication line(see copending U.S. patent application Ser. No. 06/732,004, filed May 6,1985, and assigned to the assignee of the present application).

In this previously proposed system, a communication interval formed of aplurality of master and slave transmission areas that are arranged in atime division manner is taken as one block, and this block is repeatedcyclically. The time control for communication is provided exclusivelyby the master apparatus. The number of slave apparatus transmissionareas is equal to the number of slave apparatus.

Even when two communication lines (master apparatus transmission lineand slave apparatus transmission line) are used, seen from the side ofthe slave apparatus the transmission lines appear as one. Accordingly,when the communication is carried out cyclically as described above, thetransmissions from the several slave apparatus are effected in therespective transmission areas in a time division manner.

However, since transmission areas are provided for all of the pluralityof slave apparatus in a time division manner, as the number of slaveapparatus increases, the total transmission period becomes very long.

Since each slave apparatus does not always request the master apparatusto transmit video information, if a transmission area is provided foreach of the plurality of slave apparatus as described above, anunoccupied or useless transmission area occurs, resulting in low timeefficiency.

On the other hand, it frequently happens that a mode signal, a controlsignal and a command signal are communicated between the videoinformation apparatus and the peripheral apparatus, for example, betweenthe VTR and the video camera and the editing apparatus, in order thatthe two apparatus may be operated in synchronism with each other.

In the prior art, a communication of this kind is performed regardlessof its time relation to an input signal or a reproduced video signal.For example, when a mode is changed, commands such as "playback modenext", "stop mode next" and so on are transmitted and received.

Particularly, when a communication is carried out only in a necessarycase, as when the mode is changed as described above, if amiscommunication or erroneous communication occurs, the present moderemains erroneous at least until the next communication is made forchanging the mode.

Further, since it is not known in advance exactly when the transmissiondata will arrive at the peripheral apparatus, the peripheral apparatusmust be always in an interruptible state and always in a communicablestate, so that the software therefor is difficult to write.

As to the video information apparatus, since it is not known in advanceexactly when the command or the like will arrive from the peripheralapparatus, the software therefor is also difficult to write.

For this reason, it may be concluded that the communication should becarried out cyclically. However, if the cycle or period is free-runningand not synchronized with a video signal or in a fixed time relation tothe latter, various problems occur.

For example, it has recently been proposed that data such as a time codeincluding a frame number, a field number and the like be multiplexed ona video signal and then recorded. In such case, when the time codes arecommunicated, if the communication between the VTR and the peripheralapparatus is carried out over a period longer than, for example, thevertical period, the communication surpasses the frame number or fieldnumber of the time code at a certain time, producing a dropout in thetime code input.

Furthermore, it the period of the communication is not synchronized withthe video signal, when the command (for example) "set recording mode twofields from now" is issued in a communication between the VTR and theediting apparatus, the time "two fields from now" cannot be determineduniquely. This makes the software therefor very difficult to write.

OBJECTS AND SUMMARY OF THE INVENTION

An object of this invention is to provide a bidirectional digitalcommunication system for video information apparatus that overcomes theproblems of conventional apparatus noted above.

Another object of the invention is to provide a communication system forvideo information apparatus in which time division multiplexing can beeasily controlled by an inexpensive microcomputer.

Another object of the invention is to provide a communication system inwhich the number of time division areas can be less than the number ofslave apparatus and in which the number of unused time division areascan be reduced, thereby improving time efficiency.

Another object of the invention is to provide a communication system forvideo information apparatus in which, when communication is carried outduring a constant period or vertical period, the communication intervalcan be prevented from becoming too long. This provides free time duringa .[.step.]. .Iadd.stop .Iaddend.interval that can be employed toperform functions other than communication.

Another object of the invention is to provide a communication system forvideo information apparatus that can transmit communication data signalssuch as a frame number signal and so on corresponding to the framenumber, field number or the like.

Another object of the invention is to provide a communication system forvideo information apparatus in which, since the time for starting acommunication can be predicted, the hardware of the peripheral apparatusand of the master apparatus can be simplified.

Another object of the invention is to provide a communication system forvideo information in which, since the communication is carried out insynchronism with the vertical period, it can easily be determinedwhether or not noise is mixed into a picture by the communication,thereby reducing the debugging period.

The foregoing and other objects of the invention are attained, accordingto one aspect thereof, by the provision of a system for communicatingbetween master video apparatus and peripheral apparatus wherein videosignals organized into vertical periods are processed; the apparatuscomprising: means for generating timing signals synchronously with thevertical periods; means for establishing first communication intervalshaving a substantially constant phase relation with respect to thetiming signals; and communication means for effecting communicationbetween the master apparatus and the peripheral apparatus during thefirst communication intervals.

According to another aspect of the invention, there is provided a datacommunication method for communicating serial data between a masterapparatus and a plurality of slave apparatus in a bidirectional mannercomprising the steps of: repeating cyclically a communication intervalformed of a plurality of separate communication areas, the number ofareas being less than the number of the slave apparatus; reserving firstselected ones of the areas for transmission by the master apparatus andsecond selected ones of the areas for transmission by the slaveapparatus; and respectively allocating the second areas to individualones of the slave apparatus on a first-come, first-served basis.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of these and other objects, features andadvantages of the present invention will become apparent from thefollowing detailed description of the preferred embodiment thereof inconjunction with the accompanying drawings, wherein like referencecharacters designate like elements and parts and wherein:

FIG. 1 is a block diagram of a communication system (including a VTRused as master apparatus and a video camera used as a slave apparatus)to which an embodiment of a communication method and apparatus accordingto this invention is applied;

FIG. 2 is a diagram useful for explaining a bidirectional communicationcarried out between the VTR and video camera shown in FIG. 1;

FIGS. 3A (formed of FIGS. 3A-I and 3A-II) to 3K (formed of FIGS. 3K-Iand 3K-II) are diagrams used to explain the transmission and reception,respectively, in one communication interval;

FIG. 4 is a flow chart useful for explaining the operation carried outby slave apparatus to determine an unoccupied transmission area withinwhich to transmit;

FIG. 5 is a diagram schematically illustrating the operation of the flowchart of FIG. 4;

FIG. 6 is a flow chart of a program used by the VTR;

FIG. 7 is a flow chart of a program used by the video camera;

FIGS. 8A and 8B are diagrams used to explain how to cope with thedisorder of a vertical synchronizing signal;

FIG. 9 is a flow chart helpful for explaining the operations of FIGS. 8Aand 8B; and

FIGS. 10A and 10B are respectively diagrams used to explain examples ofother communication modes, such as when a communication is carried outin the midst of one operation, so that other operations cannot beperformed and when a time division multiplexing process can becontrolled easily.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Now, the present invention will hereinafter be described with referenceto the attached drawings.

FIG. 1 is a block diagram showing an example of a communication systemto which an embodiment of a bidirectional data communication method andapparatus according to the present invention is applied. In thisexample, the bidirectional serial data communication is made possible bya single communication line. A VTR 10 (video tape recorder) is used asthe master apparatus, and more than three slave apparatus such as avideo camera 20, a television tuner unit and an editing apparatus(neither of the latter two being shown) are used. Since the structure ofthe communication control sections at the various slave apparatus areall the same, only the video camera 20 is shown in the example of FIG.1.

A data communication line 30 transmits control data between the VTR 10and the video camera 20 and other slave apparatus.

The VTR 10 comprises a control section 11 which incorporates therein amicrocomputer 110 to carry out the communication control and othercontrols, a video circuit and mechanical deck section 12, a VTR functionkey section 13, a VTR mode display section 14, a remote control functionkey section 15 for the video camera 20 and so on.

The video camera 20 comprises a control section 21 which incorporates amicrocomputer 210 to carry out a communication control and othercontrols, a camera function key section 22, a remote control functionkey section 23 for the VTR 10, a display section 24 which can displaydata within, for example, a finder of the video camera 20 and so on.Further, motors 25F and 25Z for respectively rotating a focusing ringand a zoom ring of an image pickup lens and an iris motor 25I forcontrolling the opening and closing of the iris are respectivelyconnected through motor drive circuits 26F, 26Z and 26I to the controlsection 21.

The function key section 13 of the VTR 10 includes function keys forplacing the apparatus in any of various modes, such as a recording mode,playback mode, pause mode, fast forward mode, rewind mode, stop mode andso on. When one of these function keys is depressed, the microcomputer110 of the control section 11 identifies the depression of the functionkey and displays it on the display section 14. At the same time, themicrocomputer 110 supplies a necessary control signal to the videocircuit and mechanical deck section 12 so as to place the VTR in themode corresponding to the mode of the operated function key.

Also the remote control function key section 23 for the VTR 10 at thevideo camera 20 includes function keys corresponding to various modes,such as recording mode, playback mode, pause mode, fast forward mode,rewind mode, stop mode and so on. When one of these function keys isdepressed, as described below, control data is transmitted to the VTR 10from the video camera 20 through the communication line 30. Such controldata is latched in the register of the microcomputer 110 in the controlsection 11 and then the mode of the VTR 10 is determined from thecontent of the control data and the state of the key input of thefunction key section 13 of the VTR 10 at that time. The correspondingmode is displayed on the display section 14 and the appropriate controlsignal is supplied to the video circuit and the mechanical deck section12, thus placing the VTR 10 in the corresponding mode. The reason themode of the VTR 10 is determined on the basis of the data transmittedfrom the video camera 20 and the state of the function key section 13 ofthe VTR 10 is to prevent any erroneous operation. For instance, the casewherein the video camera 20 is placed in the recording mode while theVTR 10 is placed in the fast forward mode is not normal; in such a case,therefore, a fast forward command would be neglected and the recordingmode would be continued. The correct operation is realized since themanner in which the future mode of the VTR 10 is selected in accordancewith the combination of the remote control signal and the function keymode is stored in the microcomputer 110.

The signal data indicating that the VTR 10 is placed in thecorresponding mode is then transmitted from the VTR 10 to the videocamera 20. The signal data is received by the video camera 20, and themode of the VTR 10 is displayed on the display section 24 within theview finder.

The remote control function key section 15 for the video camera 20 ofthe VTR 10 includes keys such as a focus key, iris key, zoom key, pankey, tilt key and so on. For example, when the zoom is operated, as willbe described later, zooming data is transmitted to the video camera 20from the VTR 10 through the transmission line 30 and stored in theregister of the microcomputer 210 of the control section 21 in the videocamera 20. Then, the zooming data is supplied to the zoom motor 25Zthrough the motor drive circuit 26Z, so that the zooming operation iscarried out.

If the function key section 22 in the video camera 20 is operated, thecamera 20 carries out the operation corresponding to the key operationin response to the signal from the microcomputer 210 of the controlsection 21. If, for instance, the zoom key of the video camera 20 isoperated, the zooming operation will be carried out.

The control section 11 of the VTR 10 and the control section 21 of thevideo camera 20 are constructed as described below. The control section21 is constructed in exactly the same way in the other slave apparatus.

The microcomputer 110 in the control section 11 of the VTR 10 and themicrocomputer 210 in the control section 21 of the video camera 20include 8-bit shift registers 111 and 211, respectively. Each of theshift registers 111 and 211 includes a serial input terminal SI, aserial output terminal SO and a clock terminal CK. The writing andreading of data into and from the shift registers 111 and 211 arecarried out in the form of parallel data for the data buses of themicrocomputers.

The writing and reading of the serial data into and from the shiftregisters 111 and 211 are controlled by communication controllers 112and 211 are controlled by communication controllers 112 and 212,respectively. The communication controllers 112 and 212 generate signalsG₁, G₂ and G₁ ', G₂ ' which control input gate switches 113, 213 andoutput gate switches 114, 214 to turn on and off and shift clocks CLKand CLK' (one cycle thereof is, for example, 104 μsec) for the shiftregisters 111 and 211.

The communication controller 112 provided in the VTR 10, which is usedas the master apparatus, is adapted to generate a start bit on the basisof a communication start signal CS transmitted from the microcomputer110; on the other hand, the communication controller 212 in the videocamera 20, which is used as slave apparatus, does not produce the startbit. In other words, the time control for the communication is carriedout only by the VTR 10, which functions as the masterapparatus.Iadd...Iaddend.

Microcomputers can be employed as the communication controllers 112 and212.

Transistors 115 and 215 are input transistors, while transistors 116 and216 are output transistors. The collectors of the output transistors 116and 216 are connected through resistors 117 and 217, respectively, topower supply terminals of +5 V. The same collectors are furtherconnected to the communication line 30. The emitters of the respectivetransistors 116 and 216 are grounded. The serial data from the shiftregisters 111 and 211 are supplied through the output switches 114 and214 to the bases of the output transistors 116 and 216, respectively.

The communication line 30 is connected through resistors 118 and 218 tothe bases of the input transistors 115 and 215. The emitters of theinput transistors 115 and 215 are grounded and the collectors thereofare connected through resistors 119 and 219, respectively, to the powerterminals of +5 V. The collectors of the input transistors 115 and 215are further respectively connected through input switches 113 and 213 tothe serial input terminals SI of the shift registers 111 and 211.

Accordingly, when data is not being transmitted through thecommunication line 30, the line 30, since connected to the power supplyterminals (+5 V) via the resistors 117 and 217, is maintained at a levelas high as +5 V.

In the arrangement described above, the bidirectional communicationbetween the VTR 10 as the master apparatus and the video camera 20 asthe slave apparatus is carried out in synchronism with the verticalsynchronizing signal VD shown in FIG. 2.

More specifically, in the VTR 10 as the master apparatus, an intervalformed of two receiving areas (transmitting areas of the slaveapparatus) P₁ and P₂ and two transmitting areas (receiving areas of theslave apparatus) P₃ and P₄ is treated as one communication interval.This communication interval and a pause interval of a constant periodare repeatedly transmitted in synchronism with the verticalsynchronizing signal VD as shown in FIG. 2. There are thus twotransmission areas P₁ and P₂ for the slave apparatus, so that there arefewer slave apparatus transmission areas than there are slave stations.The transmissions from the slave apparatus are carried out by using avacant one of the areas P₁ and P₂ as described below.

One bit at the beginning of each of the areas P₁, P₂, P₃ and P₄ isreserved for a start bit, which is produced only by the VTR 10 that isused as the master apparatus and by which the reception and thetransmission between the master apparatus and the slave apparatus can becarried out. That is, the communication controller 112 produces fourstart bits SB in one communication interval during each cycle.

Serial data D₀ to D₇ of 8 bits are transmitted in each of thetransmission and receiving areas P₁ to P₄ and the data D₀ to D₇ of 8bits constitute one word. Since one communication interval is formed offour communication areas P₁ to P₄, four data words are received andtransmitted during one vertical period TF. The word number and the bitnumber within the communication interval are made constant so that thelength of the communication interval becomes constant. Thus the lengthof the pause interval is also constant.

The transmission and reception within one communication interval iscarried out as follows. First the transmission from the master apparatuswill be described. While in FIG. 2 transmission from the masterapparatus is carried out after the transmission from the slave apparatusis carried out, the sequential order of the transmission and thereception does not cause any problems if it is determined in advance.

The microcomputer 110 of the master apparatus generates a communicationstart signal CS (shown in FIG. 3A) which is then supplied to thecommunication controller 112. The communication start signal CS isnormally "1" and falls off to "0" when the communication start requestis generated. In this embodiment, the communication start signal CSfalls to "0" four times during one vertical period TF. When thecommunication start request is generated, the communication controller112 produces the start bit SB (shown in FIG. B) that becomes "1" duringa period of one bit or predetermined duration of time equal, forexample, to 104 μsec. The period during which the start bit SB is highbegins when the communication start signal becomes low. This start bitSB is supplied to the base of the output transistor 116 and then issupplied to the communication line 30 which is connected with thecollector of the output transistor 116 as a signal "0" whose polarity isinverted.

The communication controller 112 generates 8 clock pulses CLK (shown inFIG. 3C) having a clock cycle or pulse period equal to 104 μsec. Thefirst of the 8 pulses commences at a time coincident with the fallingedge of .[.he.]. .Iadd.the .Iaddend.start bit SB. These pulses CLK aresupplied to the clock terminal CK of the shift register 111. The controlsignal G₁ (shown in FIG. 3D) for the output switch 114 becomes "1"during the period of 8 clock pulses CLK, and the output transistor 114is turned on during this period of "1". Since transmission data DT₁(shown in FIG. 3F) is already stored in the shift register 111 by themicrocomputer 110.Iadd., .Iaddend.the 8-bit transmission data DT₁ isread out from the shift register 111 by the 8 clock pulses CLK and thenis supplied through the output switch 114 and the output transistor 116to the communication line 30. FIG. 3G shows the state of the signal onthe communication line 30.

When the 8-bit transmission data DT₁ is transmitted, the output witch114 is turned off so that the communication line 30 is pulled up to "1".The period of "1" lasts for a time equal to the duration of 2.5 to 5bits, and the period of 2.5 to 5 bits constitutes an end bit (refer toFIGS. 2 and 3G). Such end bits are usually selected to be about twonormal bits in duration. In this embodiment, however, in order to affordsufficient time for the microcomputer to perform all operationsspecified by the software, including latching and/or storing thecommunication data in a RAM (random access memory) of the microcomputer,the stop bit is extended so that it is longer than a normal bit.

The data transmitted from the master apparatus in the transmission areaas mentioned above is supplied to, for example, the base of the inputtransistor 215 provided in the slave apparatus such as the video camera20. The input transistor 215 is turned off at the start bit SB so thatthe collector output rises to "1". The communication controller 212detects this condition, and the control signal G₁ ' (FIG. 3I) for theinput switch 213 rises to "1" and 8 clock pulses CLK' (FIG. 3K) eachhaving a cycle 104 μsec in length are produced, whereby the input switch213 is turned on and the clock pulse CLK' is supplied to the clockterminal CK of the shift register 211. As a result, the transmissiondata DT₁ from the VTR 10 is latched in the shift register 211. The datalatched in the shift register 211 is then transmitted to and stored inthe RAM (not shown) of the microcomputer 210 during the stop bit period,and data DT₂, which is to be transmitted from the video camera 20 to theVTR 10, is set in the shift register 211.

Although the data DT₁ is latched in other slave apparatussimultaneously, whether or not the other slave apparatus use the dataDT₁ is determined by their microcomputers by interpreting the content ofthe data DT₁.

The receiving area for the master apparatus, or the transmission fromthe slave apparatus will be described next.

When the video camera 20 issues the transmission command and atransmission demand signal DM (FIG. 1) is supplied to the communicationcontroller 212, the video camera 20 is set in a transmission standbymode and the transmission data DT₂ (the right-hand side of FIG. 3H) isstored in the shift register 211.

Under this state, the start bit SB (FIG. 3B) is generated by thecommunication controller 112 of the VTR 10 at the beginning of the areaP₁ (FIG. 2) and the start bit SB is transmitted through the transistor116 (FIG. 1) and the communication line 30 to the video camera 20. Then,as shown in the right-hand side of FIG. 3G, the data on the transmissionline 30 becomes "0" during one bit period. As a result, the inputtransistor 215 of the video camera 20 is turned off and the collectoroutput thereof becomes "1". Since the communication controlled 212detects this condition and the control signal G₂ ' (FIG. 3J) for theoutput switch 214 becomes "1", the output switch 214 is turned on andthe 8 clock pulses CKL' are generated during the period in which thesignal G₂ ' is "1". The 8 clock pulses CLK' are fed to the clockterminal CK of the shift register 211. Consequently, the data DT₂ isread out from the shift register 211 (refer to FIG. 3H) and is fedthrough the output transistor 216 to the communication line 30.

After the start bit SB is generated by the communication controller 112of the VTR 10, the control signal G₂ (FIG. 3E) for the input switch 113becomes "1" so that the input switch 113 is turned on and the 8 clockpulses CLK (FIG. 3C) are generated during the period in which the signalG₂ becomes "1".

Accordingly, the data DT₂ transmitted from the video camera 20 issupplied through the input transistor 115 and the switch 113 to theshift register 111 and stored in the shift register 111 on the basis ofthe clock pulse CLK.

The data DT₂ is then transferred to and stored in the RAM of themicrocomputer 110 during the end bit period of the transmission area P₁.

In the case described above the first area P₁ in the communicationinterval is not used as a transmission area by other slave apparatus.Interference between two slave apparatus competing to use the sametransmission area is avoided by causing one of the slave apparatus totransmit in the next area P₂. In other words, certain transmission areasare reserved for transmissions made by the various slave apparatus, andthese areas are respectively allocated to individual ones of the slaveapparatus on a first-come, first-served basis.

FIG. 4 is a flow chart representing a program used for such purpose. Theprogram routines conforming with the flow chart of FIG. 4 are executedby the microcomputer of the control section of each slave apparatus.

When the start bit SB is transmitted from the master apparatus to eachslave apparatus at the beginning of the area P₁, the slave apparatushaving the transmission request command transmits the transmission datato the communication lines 30 (step 101) in the transmission area P₁. Atthat time, the state of the data transmitted to the communication line30 and the .[.stat.]. .Iadd.state .Iaddend.of the communication line 30are compared at every bit (step 102). More specifically, if thetransmission data is "0", the output transistor 216 is in the off stateso that the communication line 30 must be placed in the state of 5 V,while if the transmitted data is "1", the output transistor 216 isturned on so that the communication line 30 must be placed in the stateof OV.

However, when data are transmitted from a plurality of slave apparatus,if the data bit formed any one of the slave apparatus becomes "1", sinceits output transistor 216 is turned on, the communication line 30 islowered to 0 V regardless of the data of other slave apparatus.Accordingly, when the communication line 30 becomes 0 V while the bit ofthe transmitted data is "0", an inconsistency exists between the data astransmitted and the data as monitored on the communication line 30. Thisinconsistency is detected by the microcomputer of the control section ofthe slave apparatus (step 103) and signifies the simultaneoustransmission by other slave apparatus through the same area P₁. From thepreceding description, it is apparent that when two or more slaveapparatus simultaneously transmit data through the same transmissionarea, the slave apparatus whose transmission data .[.bi.]. .Iadd.bit.Iaddend.D₀ to D₇ transmits "1" first is given priority and thecorresponding area is assigned as the transmission area of that slaveapparatus. Then, in the slave apparatus in which it is detected that thedata as transmitted and the data on the communication line 30 aredifferent from each other at a given bit, the succeeding bits are allset to "0", whereby to prevent the data of the slave apparatuspreempting the area P₁ from being transmitted incorrectly.

The slave apparatus which could not transmit data through the area P₁again transmits data on the basis of the start bit SB which occurs atthe beginning of the area P₂ (step 104). A determination whether or notthe area P₂ is vacant is made in the same way as earlier noted at steps105 and 106. If the area P₂ is vacant, it is selected as thetransmission area of that slave apparatus. If on the other hand it isoccupied, a determination whether or not the area P₁ is vacant describedabove is made again in the next cycle. The operation described above isrepeatedly carried out until a vacant area is detected.

FIG. 5 schematically illustrates these operations. In FIG. 5, a slaveapparatus 1 (for example, a tuner) and another slave apparatus II (forexample, an editing apparatus) compete with each other with respect tothe transmission demand in the area P₁ and the editing apparatus as theslave apparatus II transmissions switches into the area P₂. The matterapparatus (VTR) receives in areas P₁ and P₂ and transmits in the areasP₃ and P₄ .Iadd.. .Iaddend.Both slave apparatus receive in areas P₃ andP₄. Both attempt to transmit in the area P₁ (left half of FIG. 5). Thetuner preempts the area P₁ and the editor then switches to the area P₂(right half of FIG. 5).

The checking of the area at every bit can be performed easily by theshift register 211, which is formed as a 9-bit shift register. Inpractice, since the shift register that the 4-bit microcomputerincorporates therein is of a 9-bit type, such shift register can be usedwithout modification.

During the pause or stop interval next following the communicationinterval formed of the four areas P₁ to P₄, the data processing based onthe content of the received data is carried out by the VTR 10, the videocamera 20 and other slave apparatus, and other processing is carried outin a time division manner.

As described below, the communication interval including thetransmission from the VTR 10 and the transmission from the slaveapparatus such as the video camera 20 and the like into one block isrepeated cyclically, the pause interval being interposed therein. Inthis embodiment, since the start bit SB is generated only by the masterapparatus and the time control is carried out by the master apparatus,the areas P₁ to P₄ can be discriminated surely and the communicationinterval and the pause interval can be reliably distinguished from eachother.

These operations are executed in accordance with the following programroutines of the microcomputers of the VTR 10 and the video camera 20.

FIG. 6 is a flow chart.[.:.]. of the program steps for the VTR 10, inwhich steps 201 to 209 are executed sequentially and repeatedly. Insteps 205 to 207, either the command from the video camera 20 or thefunction key operation of the VTR 10 is given priority, whereby the modeof the VTR 10 is determined.Iadd.. .Iaddend.These steps 205 to 207 areused to prevent erroneous operation.

In step 209, data corresponding to the key operation at the VTR 10 anddata indicative of the mode of the VTR 10 designated by the remotecontrol signal from the video camera 20 are generated; and dataindicative of "no operation to be performed" is generated when there areno command and no mode to be transmitted to the video camera 20.

More particularly, at step 201, the start SB is transmitted by the VTR10 (master apparatus). At step 202, data is received. At step 203, thestart bit SB is transmitted. At step 204, data is transmitted. At step205, the received data is analyzed. At step 206, the operated functionkey of the VTR 10 is read. At step 207, the mode of the VTR 10 isdetermined. At step 208, the mode of the VTR 10 is displayed. At step209, the data to be transmitted is generated.Iadd.. .Iaddend.The programthen recycles to step 201.

FIG. 7 is a flow chart of the program routine for the video camera 20,in which steps 301 to 308 are executed sequentially and repeatedly. Instep 308, the transmission data is generated and stored in the registerand the video camera 20 is set in the standby mode until the start bitis received. The transmission data is transmitted at step 304.

More particularly, at step 301, the start SB is received by the videocamera 20 (slave apparatus). At step 302, data is transmitted. At step303, the start bit SB is received. At step 304, data is received. Atstep 305, the received data is analyzed. At step 306, the mode of thecamera 20 is displayed. At step 307, the operated function key of thecamera 20 is read. At step 308, the data to be transmitted is generated.The program then recycles to step 301.

The generation of the start bit and of the clock pulse in thecommunication controller 112 and the detection of the start bit and thegeneration of the clock pulse in the communication controller 212 may becarried out under the control of the microcomputers 110 and 210,respectively, or by other hardware, as those skilled in the art willunderstand.

The communication is carried out in synchronism with the vertical syncsignal VD as described above. When an artificial sync signal is mixedinto the vertical sync signal VD or the television channel is changed bythe television tuner, the period of vertical sync signal is disorderedtemporarily. If the communication responds to the disorder of thevertical sync signal, the communication may be interrupted, ormalfunctions may occur in processes or operations other than thecommunication.

Therefore, the following operations are performed so as to cope with thedisorder of the vertical synchronizing signal.

The following data processing is executed by the software program of themicrocomputer 110 of the VTR 10 that is used as the master apparatus forcommunication.

The VTR 10 is set in the standby mode, in which it is momentarilyinoperative, after a period S that begins at the leading edge of thevertical sync signal VD (FIG. 8A) and that is selected so that TF>S. Theperiod S may be, for example, 15 msec (see FIG. 8B). More specifically,the communication interval begins at the leading edge of the verticalsync signal VD, and the pause or stop interval, in which operationsother than communication are performed, begins at the end of the periodS. These other operations are interrupted until the time S is passedfrom the leading edge of the vertical sync signal VD. The normalcomplete cycle is 16.7 msec.

The vertical sync signal VD is not disordered, if the following verticalsync signal VD arrives at the end of the time TF, whereby the VTR 10 isreleased from its waiting mode and the communication begins (see FIG.8B). This operation is repeated indefinitely.

Generally, if the maximum waiting interval is taken as 2ΔS, the waitingmode is released at the midpoint thereof. That is, TF=S+ΔS isapproximately established.Iadd.. .Iaddend.Theoretically, TF is aconstant (16.66 . . . msec=1/60 sec), but actually it contains aperiodic error ΔT, as discussed below.

If the period of the vertical sync signal VD is disordered by channelselection and the like as shown in FIG. 8A, when the constant waitingperiod 2ΔS passes (FIG. 8B), the waiting mode is released and hence thecommunication begins.Iadd.. .Iaddend.If the vertical sync signal VDarrives before 3 msec passes (following the end of period S), thewaiting mode is released upon its arrival: i.e., the waiting mode isreleased without waiting for the full 3 msec. Thus, the VTR 10 isdesigned to follow the disorder of the period of the vertical syncsignal VD if the time displacement of the vertical sync signal VD doesnot exceed ±ΔS. However, when the disorder of the period of the verticalsync signal VD is such that the time displacement thereof exceeds ±ΔS,the VTR 10 is not synchronized with the vertical sync signal VD for acertain time duration and the free-running cycle of duration S+2ΔS thatis determined by the microcomputer 110 continues. Thereafter, when thevertical sync signal VD again enters into the waiting period of 2ΔS,communication is started in synchronism with the vertical sync signalVD.

That is, when the vertical sync signal VD is disordered, a window havinga width of ±ΔS is provided for the vertical sync signal VD. Accordingly,disorder of the synchronization is known to exist when the vertical syncsignal VD is outside this window. Then, until the vertical sync signalenters into the window, the communication is carried out at thefree-running cycle of S+2ΔS. The time required by the VTR 10 to returnto synchronization with the vertical sync signal VD is determined by thewidth 2ΔS of the window. In FIG. 8 two successive vertical sync signalsVD are shown to occur with a period X₁ that deviates considerably fromthe norm. If the periodic error of the vertical sync signal VD is takenas ±ΔT where ΔS>T and the displacement between the vertical sync signalVD and the communication cycle after the channel is changed is taken asX₂, the following equation results: ##EQU1##

The displacement is thus reduced by (ΔS±ΔT) at every period and hence inthe worst case the vertical sync signal VD again enters into the windowafter a period of ##EQU2## and the VTR 10 is located to the verticalsync signal VD. These operations are carried out in accordance with theflow chart of FIG. 9. At step 401, the timer is cleared. At step 402,communication and other processes are carried out. At step 403, adetermination is made whether or not the value registered by the timerhas reached the starting point of the window. The determination is maderepeatedly until the answer is yes. At step 404 a determination is madewhether or not the sync signal has arrived. If so the program loops backto step 401. If not a determination is made at step 405 whether or notthe value registered by the timer has reached the end point of thewindow. As long as the end point of the window has not been reached, theprogram loops back to step 404; when the end point of the window isreached, the program loops back to step 401.

As described above, when a PLL circuit is constructed by the software ofthe microcomputer, the communication can be carried out in synchronismwith the vertical sync signal VD.

Accordingly, if the vertical sync signal VD is .Iadd.disordered rapidlyor the sync signal is weakened to destroy .Iaddend.the synchronization,free-running synchronization is established by the PLL circuit providedby the software of the microcomputer so that interruption ofcommunication is prevented and the communication therefore follows thevertical sync signal VD.

Since the processing time for transmission .[.an.]. .Iadd.and.Iaddend.reception is provided by making the length of the end bitlonger than the norm, the serial data can be read out and written easilyby the software. In addition, with respect to the hardware, there is theadvantage than an extra latch circuit is not required.

Further, this system is an excellent match for the RS-232C that is thecommunication interface standard widely used in apparatus of this kind.In the communication system of this embodiment, using the RS-232C systemcommunication channel, the data can be read out only by voltageconversion.

Since the communication is carried out cyclically and can befree-running, the correct content of the communication is restoredimmediately in case of a dropout or inadvertent error in thecommunication.

Furthermore, only the transmission line is needed, an expensiveinterface is not used, the communication and related functions can allbe carried out by a one-chip microcomputer, and bidirectional digitaldata communication can be realized by inexpensive home LSIs.

In addition, since synchronization of the communication is establishedby the master apparatus, even when a plurality of operations A, B, C andD (FIG. 10A and 10B) in addition to the communication must be performedin a time division manner, it is possible to prevent a given operationfrom being interrupted while in progress.

That is, when synchronization of the communication is not establishedand an expensive interface is not employed, the communications may becarried out in the midst of one operation as shown in FIG. 10A so thatother operations cannot be carried out. In this embodiment, since thesynchronization of the communication is established by the masterapparatus and other operations are carried out in the pause or stopinterval of constant length, the control of the time divisionmultiplexing processing becomes easy as shown in FIG. 10B. As a result,there is the advantage that the signal processing can be carried out byan inexpensive microcomputer.

In the embodiment described above, the communication is started insynchronism with the vertical sync signal VD itself; alternatively,communication may be started in synchronism with a signal synchronizedwith the vertical sync signal: for example, a signal indicative of therotary phase of a rotary head and a switching signal for two rotaryheads.

While the embodiment described above is the special case wherecommunication can be realized by a single communication line, thepresent invention can be applied also to a case where two lines fortransmission and reception, respectively, extend from the masterapparatus to a plurality of slave apparatus.

While in the embodiment described above a check is made at intervals ofone bit to determine whether or not the transmission area is vacant, acheck may be made at intervals of, for example, one word (8 bits).

If in the embodiment of FIG. 2 the earlier areas P₁ and P₂ are assignedas transmission periods of the slave apparatus and the later areas P₃and P₄ are assigned as transmission periods of the master apparatus,only the start bit of the first half can always be transmittedcyclically, while the start bit of the second half can be transmittedonly when data is transmitted from the master apparatus. Further, if thereception of incoming data is carried out before the transmission ofoutgoing data, it is possible to reduce considerably the buffer memoriesthat store the data in the communication controller 212 and themicrocomputer 210 of the slave apparatus.

In accordance with the present invention, since the transmission fromthe slave apparatus is carried out by using a selected unoccupied areaof the plurality of time division areas, the number of time divisionareas can be smaller than the number of slave apparatus; in addition,the unused areas are reduced and the efficiency of use is increased.Furthermore, when the communication is carried out at a constant period,for example the vertical period, it is possible to prevent the length ofthe communication interval from becoming too long. Accordingly, it ispossible to preserve the time necessary for carrying out operationsother than communication during the stop mode interval.Iadd.. .Iaddend.

Further, according to the present invention, since the communication iscarried out periodically, if the communication is carried out onceerroneously, the correct data is transmitted on the next occasion,whereby the erroneous communication is restored to the correct one. Inaddition, according to the present invention, since the communication iscarried out in synchronism with a signal synchronized with the verticalsync signal.Iadd., .Iaddend.it is possible to transmit as communicationdata signals corresponding to the frame number and field of the videosignal.

Furthermore, since the communication timing can be predicted, the designof the hardware of the peripheral apparatus and the main body issimplified.

In addition, since the communication is carried out in synchronism withthe vertical period, the mixing of noise into the picture due to thecommunication or the like can be detected easily and the debuggingperiod is reduced.

Thus there is provided in accordance with the invention a novel andhighly effective method and apparatus for communication between videoinformation apparatus, such as a VTR or video disc player, andperipheral apparatus, such as a tuner, a timer, a video camera, editingapparatus, a computer and so on. Many modifications of the preferredembodiment of the invention described above will readily occur to thoseskilled in the art without departing from the spirit or scope of theinvention. Accordingly, the invention is defined by the appended claimsonly.

We claim: .[.
 1. A system for communicating between master videoapparatus and a plurality of peripheral apparatus wherein video signalsorganized into vertical periods of successive fields are processed; saidsystem comprising:means for generating timing signals synchronously withsaid vertical periods; means for establishing first communicationintervals having a substantially constant phase relation with respect tosaid timing signals; communication means for effecting communicationbetween said master apparatus and said peripheral apparatus during saidfirst communication intervals; said first communication intervals beingdivided into separate transmission areas, a plurality of saidtransmission areas being reserved for transmission of communications bysaid peripheral apparatus, the number of said reserved areas being lessthan the number of said peripheral apparatus; and means independent ofsaid master apparatus whereby one of said peripheral apparatus canpreempt one of said reserved areas for transmission therein..].
 2. Asystem .[.according to claim 1; further comprising.]. .Iadd.forcommunicating bidirectionally between a master video apparatus and aperipheral apparatus wherein video signals having vertical sync signalsare processed and a single transmission line connects said master videoapparatus and said peripheral apparatus, said systemcomprising.Iaddend.:.Iadd.means for generating timing signalssynchronously with said vertical periods; means for establishing firstcommunication intervals having a substantially constant phase relationwith respect to said timing signals; communication means forperiodically and repeatedly effecting communication between said masterapparatus and said peripheral apparatus through said one transmissionline during said first communication interval; .Iaddend. means forestablishing a window within which said timing signals normally appear;.detecting means for detecting the presence of said timing signals withinsaid window; free-running timing means for establishing secondcommunication intervals; and means responsive to failure of saiddetecting means to detect said timing signals within said window fortemporarily substituting said second communications intervals for saidfirst communication intervals, whereby said communication temporarilytakes place during the second communication intervals.
 3. A systemaccording to claim 2; wherein said first and second intervalsrespectively have periods such that, in case of communication in saidsecond intervals, said timing signals ultimately reappear within saidwindow and said communication then takes place in said first intervals.4. A system .[.according to claim 1; further comprising a transmissionline connecting said master apparatus with each of said peripheralapparatus.]. .Iadd.for communicating bidirectionally between a mastervideo apparatus and a plurality of peripheral apparatus wherein videosignals having vertical sync signals are processed and a singletransmission line connects said master video apparatus with each of saidperipheral apparatus, said system comprising:means for generating timingsignals synchronously with said vertical periods; means for establishingfirst communication intervals having a substantially constant phaserelation with respect to said timing signals; communication means forperiodically and repeatedly effecting communication between said masterapparatus and said peripheral apparatus through said one transmissionline during said first communication interval; said first communicationintervals being divided into separate transmission areas, a plurality ofsaid transmission areas being reserved for transmission ofcommunications by said peripheral apparatus, .Iaddend.and.Iadd.preempting means independent of said master apparatus whereby oneof said peripheral apparatus can preempt one of said reserved areas fortransmission therein, .Iaddend.wherein said preempting means.[.comprises.]. .Iadd.including .Iaddend.means in each of saidperipheral apparatus for monitoring the state of said transmission line,for comparing the state thereof with the data transmitted thereto, andfor terminating transmission in said area in case of a discrepancybetween the state of said transmission line and the state of datatransmitted thereto.
 5. A system according to claim 4, wherein saidtransmitted data consists of bits representing "0's" and "1's" and saidtransmission line assumes two states respectively in accordance withsaid "0's" and "1's", and in case of competing transmissions by two ofsaid peripheral apparatus in the same transmission area, where one ofsaid periperal apparatus transmits a "0" and another of said peripheralapparatus transmits a "1", the state of said line follows a selected bitrepresenting one of said "0" and "1" in preference to the other, the oneof said peripheral apparatus having transmitted the selected bitpreempting said transmission area and the other of said peripheralapparatus yielding said transmission area.
 6. A system according toclaim 5; wherein transmission of a "1" by one of said peripheralapparatus grounds said transmission line, whereby simultaneoustransmission of a "0" by any other of said peripheral apparatus resultsin an inconsistency between said data transmitted by such other of saidperipheral apparatus and the state of said transmission line, causingsaid one of said peripheral apparatus to preempt said transmission areaand said other of said peripheral apparatus to yield said transmissionarea. .Iadd.
 7. A system for communicating between a master videoapparatus and at least one peripheral apparatus wherein video signalsorganized into vertical periods of successive fields are processed; thesystem comprising:means for generating timing signals synchronous withthe vertical periods of the video signals; means for establishing afirst communication interval having a first communication area and atleast one second communication area and wherein the first communicationinterval is repeated periodically with substantially constant phaserelationship to the timing signals; communication means for effectingcommunication between the master video apparatus and the peripheralapparatus during the first communication interval, wherein the mastervideo apparatus and at least one of the peripheral apparatus transmitduring the first and second communication areas respectively; andwherein the number of the second communication areas to be used fortransmission in the first communication intervals is less than or equalto the number of the peripheral apparatus. .Iaddend.